1. Field of the Invention
This invention relates to computers and, more particularly, to methods and apparatus for accelerating store operations in reduced instruction set computers.
2. History of the Prior Art
The development of digital computers progressed through a series of stages beginning with processors which were able to process only a few basic instructions and in which the programming needed to be done at a machine language level. Development continued to a point where processors were capable of handling very complicated instructions written in high level languages. At least one of the reasons for this development is that high level languages are easier for programmers to use, thereby rapidly increasing the development of new programs. Another reason is that up to some point in the development of digital computers the more advanced machines were capable of executing operations more rapidly.
There came a point, however, where the constant increase in the ability of the computers to run more complicated instructions actually began to slow the operation of the computer over what investigators felt was possible with machines operating with only a small number of basic instructions. These investigators began to design advanced machines for running a limited number of instructions, a so-called reduced instruction set, and were able to demonstrate that these machines did, in fact, operate more rapidly for some types of operations. Thus began the reduced instruction set computer which has become known by its acronym, RISC.
The central processing unit of the typical RISC computer is very simple. It fetches an instruction every clock cycle. In its simplest embodiment, all instructions except for load and store act upon internal registers within the central processing unit. A load instruction is used to fetch data from external memory and place it in an internal register, and a store instruction is used to take the contents of an internal register and place it in external memory. RISC processors obtain higher speeds of operation by pipelining the instructions. Processors utilized to provide pipelined operations normally cycle through fetch, decode, execute, and write back steps of operation in executing each instruction. In a typical pipelined system, the individual instructions are overlapped so that an instruction executes once each clock cycle of the system.
One design of RISC computer is based on the Scalable Process Architecture (SPARC) designed by Sun Microsystems, Inc., Mountain View, Calif., and implemented in the line of SPARC computers manufactured by that company. One salient feature of the SPARC computers is the thirty-two bit instruction word used. As with most computers, instructions have addresses which direct you to particular positions in the computer and commands which tell the computer what to do. Essentially, an instruction directs the processor to perform an operation on the contents of the registers addressed by that instruction. In a SPARC computer, an instruction includes register addresses and commands. The normal instruction (called a register+register instruction) specifies two addresses of registers to be read, an operation to be performed on the data at those register addresses, and the address of a register in which the results of the operation are to be placed. Such instructions require that the register file associated with the computer have two read ports and one write port. As with other RISC computers, in none of these normal instructions does the processor of the SPARC computer go off-chip; it simply operates with information in the register file.
However, a load or store instruction is used to get data from memory or store it to memory. Such load and store instructions thus require the processor to access off-chip memory. The SPARC instructions accomplish this by designating two register addresses at which data is found. This data is added to form a memory address (as contrasted to a register address). For a load instruction, a third address designates the register to which the data at the memory address is to be written. For a store instruction, however, a third address designates the register which holds the information which is to be written to the addressed memory location. Thus, while most instructions in a SPARC computer are set up to read two registers and write to a third register, a store instruction reads three registers, two to determine a memory address, and the third to retrieve the data to be written to the addressed memory location. Hence, the store instruction requires three read ports since the third register must be read rather than written to derive the data to be stored.
Adding a read port is expensive. For this reason, SPARC computers typically execute a store operation in two clock cycles in order to obviate the need for an extra read port. During the first cycle, the first two registers are read and the memory address computed. During the second cycle, data from the register designated by the third address field is read out through one of the two read ports. This, of course, slows the operation of the computer.